1. Field of the Invention
This invention relates generally to magnetic random access memory (MRAM) and more particularly to MRAM with units or stacks of multiple memory cells for producing more than two logic states.
2. Description of the Related Art
MRAM with magnetic tunnel junction (MTJ) memory cells has been proposed for nonvolatile memory, as described in U.S. Pat. No. 5,640,343 and by Reohr et al., “Memories of Tomorrow”, IEEE CIRCUITS & DEVICES MAGAZINE, September 2002, pp. 17–27. In these devices the MTJ cells are arranged as an array in a single layer (the X-Y plane) on a semiconductor substrate. In one type of architecture, called a 1T1MTJ MRAM (one transistor and one MTJ), each MTJ cell is located between a bit line and a transistor, with the word lines located beneath the MTJ cells. In another type of architecture, called a cross-point (XPC) MRAM, the MTJ cells are located directly between the bit and word lines.
In both MRAM architectures, a selected MTJ cell is programmed or “written”, i.e., its magnetic state or +/−X magnetization direction is switched, by write currents passing in X and Y directions through the bit and word lines (the write lines) located above and below the selected MTJ cell. The write currents generate orthogonal magnetic fields in the X and Y directions that switch the magnetization direction of the selected MTJ cell. The typical writing scheme is a “half-select” scheme, where each of the bit and word lines generates half the required write field for switching the selected MTJ cell. However, the energized bit and word lines reduce the magnetic reversal energy barrier in the other cells along their respective bit and word lines. This makes these “half-selected” cells more susceptible to having their magnetic states switched when the selected cell is written.
MRAM with units or stacks of multiple memory cells located between the write lines to produce more than two magnetic states, and thus more than two logic states, have been proposed. Examples of this type of MRAM are described in U.S. Pat. Nos. 5,930,164; 6,169,689 B1; 6,590,806 B1; and 6,801,451 B2; and in Published Patent Application US 2002/0036331 A1. In the prior art MRAM with multiple-memory-cell stacks, the write currents must be kept within relatively narrow margins to avoid writing cells in non-selected stacks. In addition, writing to the cells in a selected stack requires both a series of write pulses and write pulses with different current values, which increases both the complexity of the write circuitry and the time to write.
What is needed is an MRAM with multiple-memory-cell stacks that has increased write-current margins, less complex write circuitry and reduced write time.